Automated test systems (ATS) are generally used for testing electronic assemblies. These electronic assemblies may take the form of a line replaceable unit (LRU) or shop replaceable unit (SRU). Typically, LRUs are higher level assemblies that contain a plurality of smaller SRUs. These test systems (also referred to as testers or test stations) are populated with various pieces of automatic test equipment (ATE) in the form of stand-alone (aka ‘rack and stack’) or modular (i.e., VXI, PXI, etc.) instrumentation. These test systems may be specialized (able to test one specific assembly or family of assemblies for a specific electronics platform) or general purpose (able to test a broad range of electronics) in nature.
The software that runs the ATS is typically referred to as a runtime system and test executive which provides a testing hierarchy in the form of a testplan, entry point(s) and teststeps. A test program set (TPS) implements the entry point(s) and teststeps and typically targets a specific assembly (also referred to as a unit under test or UUT). Each teststep typically executes and evaluates a single performance test. An entry point is a group of teststeps that share a common function such as transmit, receive, etc. The testplan specifies the entry points that are executed on the assembly. The test executive allows teststeps and/or entry points to be bypassed or looped, and handles the overall operation/flow of the TPS. Coding of a TPS can take months or even years to write and integrate depending on the complexity of the UUT.
Current test stations typically include a significant arsenal of instrumentation and specialized equipment connected through a mass terminated patch panel that can connect/disconnect a 1000 or more signals at once. While this approach permits coverage across a broad range of electronics assemblies, it does have drawbacks. Most test stations implement some form of mechanical switching to route signals to/from the equipment. As test stations age, these switching elements tend to degrade, resulting in operational intermittency, higher insertion loss and lower isolation which can affect test measurements. A mass terminated patch panel is rather large and expensive, and not suited for testing the input/output (I/O) count of smaller assemblies.
A smaller, more nimble tester is more appropriate for these types of assemblies. High speed analog-to-digital conversion (ADC) technologies have advanced to the point where parallel signal capture at sufficient bandwidth, resolution and density can reliably support test program set (TPS) development using a parallel digitizing approach. Simultaneous asset use using a parallel test approach allows testing of multiple signal nodes at once resulting in a substantial reduction in test program set (TPS) runtime when compared against the traditional serial functional test approach.
A TPS is typically developed using OEM data such as acceptance test procedure (ATP), theory of operation, manuals, schematics or other relevant data. Often electronics assemblies remain in service long beyond their design life. In instances where this is the case, the original support equipment may be nearing (or even beyond) the end of its planned lifecycle, unable to test these legacy assemblies. In other instances, the ability to test these assemblies may no longer exist, resulting in an ‘orphan’ assembly. This can be further compounded by the lack of original equipment manufacturer (OEM) data or even cases where the OEM is now a defunct entity. The absence of UUT data can substantially increase the TPS effort and in some cases prevent implementation of a TPS altogether. In these situations, the traditional top down TPS approach falls short and a different approach is necessary. The invention disclosed herein departs from the traditional serial TPS structure and implements a heuristic simultaneous parallel response in combination with a ‘known good’ or ‘golden’ UUT to establish an operating characteristic response baseline.